Kategoriler
yeni
Ürün Kodu: 817803
Stok Durumu: 100
37,97 TL

PFS154

SSOP-8 

Tekrar programlanabilir (Flash)

Program hafızası  2KWord  

RAM  128 byte

2 adet 8-bit Timer

1 adet 16-bit Timer

1 adet Comparator

4 adet VDD/2 (LCD)

2 adet harici interrupt girişi


PFS154 PDF dökümanına ulaşmak için tıklayın

Padauk Mini-C veya ASM compiler içeren IDE  programı için (aşağıdaki resimdeki gibi) tıklayın

PFS154 ile ilgili faydalı linkler için tıklayın

SDCC için tıklayın

Code::Blocks programın indirmek için tıklayın 

Faydalı Dökümanlar - Genel Bakış için tıklayın

PFS154 ile yapılan bazı projeler için tıklayın

 PFS154 free programmer için tıklayın

Örnek Kod : PA7 pinine bağlı butona basıldığında PA3 pinindeki LEDi yakan program.



PADAUK FPPA core devices (14 bit) ASSEMBLY CODES

These devices feature a 14-bit wide code memory. Byte order is little endian. The instruction set is called SYM_85A in Padauk include files. The SDCC backend is called pdk14.

&
14-bit FPPA instruction set
Hex 1
3		 1
2		 1
1		 1
0
9
8
7
6
5
4
3
2
1
0		 Mnemonic ZF
?		 CF
?		 AC
?		 OV
?		 Description
0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP No operation
0x0006 0 0 0 0 0 0 0 0 0 0 0 1 1 0 LDSPTL A ← LowByte@CodeMem(WORD[SP])
0x0007 0 0 0 0 0 0 0 0 0 0 0 1 1 1 LDSPTH A ← HighByteB@Codemem(WORD[SP])
0 0 0 0 0 0 0 1 1 opcode Miscellaneous instructions
0x0060 0 0 0 0 0 0 0 1 1 0 0 0 0 0 ADDC A ZF CF AC OV A ← A + CF
0x0061 0 0 0 0 0 0 0 1 1 0 0 0 0 1 SUBC A ZF CF AC OV A ← A - CF
0x0062 0 0 0 0 0 0 0 1 1 0 0 0 1 0 IZSN A ZF CF AC OV Increment A and skip next instruction if A is zero
0x0063 0 0 0 0 0 0 0 1 1 0 0 0 1 1 DZSN A ZF CF AC OV Decrement A and skip next instruction if A is zero
0x0064 0 0 0 0 0 0 0 1 1 0 0 1 0 0 ?
0x0065 0 0 0 0 0 0 0 1 1 0 0 1 0 1 ?
0x0066 0 0 0 0 0 0 0 1 1 0 0 1 1 0 ?
0x0067 0 0 0 0 0 0 0 1 1 0 0 1 1 1 PCADD A Add A to PC
0x0068 0 0 0 0 0 0 0 1 1 0 1 0 0 0 NOT A ZF A ← ~A
0x0069 0 0 0 0 0 0 0 1 1 0 1 0 0 1 NEG A ZF A ← NEG(A)
0x006A 0 0 0 0 0 0 0 1 1 0 1 0 1 0 SR A CF A ← A >> 1
0x006B 0 0 0 0 0 0 0 1 1 0 1 0 1 1 SL A CF A ← A << 1
0x006C 0 0 0 0 0 0 0 1 1 0 1 1 0 0 SRC A CF A ← CF:A >> 1
0x006D 0 0 0 0 0 0 0 1 1 0 1 1 0 1 SLC A CF A ← A:CF << 1
0x006E 0 0 0 0 0 0 0 1 1 0 1 1 1 0 SWAP A Swap the high nibble and low nibble of A
0x006F 0 0 0 0 0 0 0 1 1 0 1 1 1 1 ?
0x0070 0 0 0 0 0 0 0 1 1 1 0 0 0 0 WDRESET Reset Watchdog timer
0x0071 0 0 0 0 0 0 0 1 1 1 0 0 0 1 ?
0x0072 0 0 0 0 0 0 0 1 1 1 0 0 1 0 PUSHAF Push A and flags to stack: [SP] ← A, [SP + 1] ← F, SP ← SP + 2
0x0073 0 0 0 0 0 0 0 1 1 1 0 0 1 1 POPAF ZF CF AC OV Pop A and flags from stack: SP ← SP + 2, F ← [SP + 1], [SP] ← A
0x0074 0 0 0 0 0 0 0 1 1 1 0 1 0 0 ?
0x0075 0 0 0 0 0 0 0 1 1 1 0 1 0 1 RESET Reset the whole chip
0x0076 0 0 0 0 0 0 0 1 1 1 0 1 1 0 STOPSYS System halt (OSC disabled)
0x0077 0 0 0 0 0 0 0 1 1 1 0 1 1 1 STOPEXE CPU halt (OSC active to output clock, SYSCLK disabled to save power)
0x0078 0 0 0 0 0 0 0 1 1 1 1 0 0 0 ENGINT Global interrupt enbale
0x0079 0 0 0 0 0 0 0 1 1 1 1 0 0 1 DISGINT Global interrupt disable
0x007A 0 0 0 0 0 0 0 1 1 1 1 0 1 0 RET Return from subroutine
0x007B 0 0 0 0 0 0 0 1 1 1 1 0 1 1 RETI Return from interrupt
0x007C 0 0 0 0 0 0 0 1 1 1 1 1 0 0 MUL Multiply (if available)
0x007D 0 0 0 0 0 0 0 1 1 1 1 1 0 1 ?
0x007E 0 0 0 0 0 0 0 1 1 1 1 1 1 0 ?
0x007F 0 0 0 0 0 0 0 1 1 1 1 1 1 1 ?
0 0 0 0 0 c 6-bit IO addr Operations with A and IO
0x00C.
0x00D.
0x00E.
0x00F.		 0 0 0 0 0 0 1 1 IO XOR IO, A IO ← IO ^ A (if available)
0x01.. 0 0 0 0 0 1 1 0 IO MOV IO, A IO ← A
0x01.. 0 0 0 0 0 1 1 1 IO MOV A, IO ZF A ← IO
0 0 0 0 1 0 8-bit immediate Return with A
0x02.. 0 0 0 0 1 0 k RET k A ← k and return from subroutine
0 0 0 0 1 1 c 7-bit MEM addr c 16 bit memory operations
0x03.. 0 0 0 0 1 1 0 M 0 STT16 M Timer16 ← M (last bit of M set to 0, M must be word aligned)
0x03.. 0 0 0 0 1 1 0 M 1 LDT16 M M ← Timer16 (last bit of M set to 1, M must be word aligned)
0x03.. 0 0 0 0 1 1 1 M 0 IDXM M, A [M] ← A (last bit of M set to 0, M must be word aligned, 2 cycles)
0x03.. 0 0 0 0 1 1 1 M 1 IDXM A, M A ← [M] (last bit of M set to 1, M must be word aligned, 2 cycles)
0 0 0 1 0 bit pos 6-bit IO addr Special operation with CF and IO
0x04..
0x05..		 0 0 0 1 0 n IO SWAPC IO.n CF Swap bit IO.n with CF
0 0 opcode 7-bit MEM addr Operations with A and memory
0x06.. 0 0 0 1 1 0 0 M COMP A, M ZF CF AC OV Compare A with M (flags changed according to (A-M)) (if available)
0x06.. 0 0 0 1 1 0 1 M COMP M, A ZF CF AC OV Compare M with A (flags changed according to (M-A)) (if available)
0x07.. 0 0 0 1 1 1 0 M NADD A, M ZF CF AC OV A ← M + NEG(A) (if available)
0x07.. 0 0 0 1 1 1 1 M NADD M, A ZF CF AC OV M ← NEG(M) + A (if available)
0x08.. 0 0 1 0 0 0 0 M ADD M, A ZF CF AC OV M ← M + A
0x08.. 0 0 1 0 0 0 1 M SUB M, A ZF CF AC OV M ← M - A
0x09.. 0 0 1 0 0 1 0 M ADDC M, A ZF CF AC OV M ← M + A + CF
0x09.. 0 0 1 0 0 1 1 M SUBC M, A ZF CF AC OV M ← M - A - CF
0x0A.. 0 0 1 0 1 0 0 M AND M, A ZF M ← M & A
0x0A.. 0 0 1 0 1 0 1 M OR M, A ZF M ← M | A
0x0B.. 0 0 1 0 1 1 0 M XOR M, A ZF M ← M ^ A
0x0B.. 0 0 1 0 1 1 1 M MOV M, A M ← A
0x0C.. 0 0 1 1 0 0 0 M ADD A, M ZF CF AC OV A ← A + M
0x0C.. 0 0 1 1 0 0 1 M SUB A, M ZF CF AC OV A ← A - M
0x0D.. 0 0 1 1 0 1 0 M ADDC A, M ZF CF AC OV A ← A + M + CF
0x0D.. 0 0 1 1 0 1 1 M SUBC A, M ZF CF AC OV A ← A - M - CF
0x0E.. 0 0 1 1 1 0 0 M AND A, M ZF A ← A & M
0x0E.. 0 0 1 1 1 0 1 M OR A, M ZF A ← A | M
0x0F.. 0 0 1 1 1 1 0 M XOR A, M ZF A ← A ^ M
0x0F.. 0 0 1 1 1 1 1 M MOV A, M ZF A ← M
0 1 0 opcode 7-bit MEM addr Operations with memory
0x10.. 0 1 0 0 0 0 0 M ADDC M ZF CF AC OV M ← M + CF
0x10.. 0 1 0 0 0 0 1 M SUBC M ZF CF AC OV M ← M - CF
0x11.. 0 1 0 0 0 1 0 M IZSN M ZF CF AC OV M ← M + 1 , skip next instruction if M is 0
0x11.. 0 1 0 0 0 1 1 M DZSN M ZF CF AC OV M ← M - 1 , skip next instruction if M is 0
0x12.. 0 1 0 0 1 0 0 M INC M ZF CF AC OV M ← M + 1
0x12.. 0 1 0 0 1 0 1 M DEC M ZF CF AC OV M ← M - 1
0x13.. 0 1 0 0 1 1 0 M CLEAR M M ← 0
0x13.. 0 1 0 0 1 1 1 M XCH M Exchange A with M
0x14.. 0 1 0 1 0 0 0 M NOT M ZF M ← ~M
0x14.. 0 1 0 1 0 0 1 M NEG M ZF M ← NEG(M)
0x15.. 0 1 0 1 0 1 0 M SR M CF M ← M >> 1
0x15.. 0 1 0 1 0